<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>Device Usage Page (usage_statistics_webtalk.html)</H3>This HTML page displays the device usage statistics that will be sent to Xilinx.<BR>To see the actual file transmitted to Xilinx, please click <A HREF="./usage_statistics_webtalk.xml">here</A>.<BR><BR><HR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
  <TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>2086221</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Wed Feb 17 23:31:23 2021</TD>
  <TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>WIN64</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>Vivado v2017.4 (64-bit)</TD>
  <TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>74faa200f74f4903b59568751ac1574a</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>3</TD>
  <TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>de6d8d3d6e335cb1ac500c3d69636505</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>de6d8d3d6e335cb1ac500c3d69636505</TD>
  <TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>TRUE</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>xc7z010</TD>
  <TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>zynq</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>clg400</TD>
  <TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>-1</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>Vivado</TD>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>Intel(R) Core(TM) i7-9750H CPU @ 2.60GHz</TD>
  <TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>2592 MHz</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>Microsoft Windows 8 or later , 64-bit</TD>
  <TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>major release  (build 9200)</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>25.000 GB</TD>
  <TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>1</TD>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
<TR ALIGN='LEFT'>  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>gui_handlers</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>abstractfileview_reload=4</TD>
   <TD>addhdlwrapperdialog_this_option_will_make_copy=8</TD>
   <TD>basedialog_ok=38</TD>
   <TD>basedialog_yes=3</TD>
</TR><TR ALIGN='LEFT'>   <TD>clkconfigtreetablepanel_clk_config_tree_table=15</TD>
   <TD>cmdmsgdialog_ok=9</TD>
   <TD>constraintschooserpanel_add_existing_or_create_new_constraints=1</TD>
   <TD>constraintschooserpanel_create_file=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>coretreetablepanel_core_tree_table=10</TD>
   <TD>createconstraintsfilepanel_file_name=1</TD>
   <TD>createnewdiagramdialog_design_name=1</TD>
   <TD>creatersbportdialog_create_vector=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>creatersbportdialog_direction=2</TD>
   <TD>creatersbportdialog_from=2</TD>
   <TD>creatersbportdialog_port_name=3</TD>
   <TD>creatersbportdialog_type=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>ddrconfigtreetablepanel_ddr_config_tree_table=3</TD>
   <TD>expruntreepanel_exp_run_tree_table=17</TD>
   <TD>filesetpanel_file_set_panel_tree=157</TD>
   <TD>filesetpanel_messages=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>flownavigatortreepanel_flow_navigator_tree=8</TD>
   <TD>gensettingtreetablepanel_gen_setting_tree_table=8</TD>
   <TD>hacgctextfield_value_of_specified_parameter=1</TD>
   <TD>mainmenumgr_export=7</TD>
</TR><TR ALIGN='LEFT'>   <TD>mainmenumgr_file=12</TD>
   <TD>mainmenumgr_help=2</TD>
   <TD>mainmenumgr_open_recent_file=4</TD>
   <TD>mainmenumgr_open_recent_project=5</TD>
</TR><TR ALIGN='LEFT'>   <TD>mainmenumgr_view=1</TD>
   <TD>mainmenumgr_window=2</TD>
   <TD>maintoolbarmgr_run=1</TD>
   <TD>mainwinmenumgr_layout=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>mioconfigtreetablepanel_mio_config_tree_table=29</TD>
   <TD>miotablepagepanel_mio_table=13</TD>
   <TD>msgtreepanel_discard_user_created_messages=1</TD>
   <TD>msgtreepanel_message_severity=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>msgtreepanel_message_view_tree=4</TD>
   <TD>newexporthardwaredialog_include_bitstream=5</TD>
   <TD>notificationmanager_run_failed=2</TD>
   <TD>pacommandnames_add_sources=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_auto_connect_ports=17</TD>
   <TD>pacommandnames_auto_update_hier=29</TD>
   <TD>pacommandnames_close_hardware_design=1</TD>
   <TD>pacommandnames_create_top_hdl=9</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_export_hardware=2</TD>
   <TD>pacommandnames_generate_composite_file=11</TD>
   <TD>pacommandnames_ip_settings=1</TD>
   <TD>pacommandnames_launch_hardware=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_open_target_wizard=1</TD>
   <TD>pacommandnames_ports_window=1</TD>
   <TD>pacommandnames_regenerate_layout=8</TD>
   <TD>pacommandnames_reports_window=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_reset_composite_file=5</TD>
   <TD>pacommandnames_run_bitgen=4</TD>
   <TD>pacommandnames_run_synthesis=1</TD>
   <TD>pacommandnames_save_design=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_save_rsb_design=3</TD>
   <TD>pacommandnames_validate_rsb_design=6</TD>
   <TD>paviews_code=14</TD>
   <TD>programdebugtab_open_target=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>progressdialog_background=1</TD>
   <TD>project_automatic_update_and_compile_order=3</TD>
   <TD>project_automatic_update_manual_compile_order=3</TD>
   <TD>projecttab_close_design=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>rdicommands_copy=5</TD>
   <TD>rdicommands_delete=3</TD>
   <TD>rdicommands_line_comment=2</TD>
   <TD>rdicommands_paste=3</TD>
</TR><TR ALIGN='LEFT'>   <TD>rdicommands_properties=1</TD>
   <TD>rdicommands_save_file=2</TD>
   <TD>removesourcesdialog_also_delete=1</TD>
   <TD>rsbapplyautomationbar_run_block_automation=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>rsbexternalinterfaceproppanels_name=6</TD>
   <TD>rsbexternalportproppanels_name=24</TD>
   <TD>saveprojectutils_save=1</TD>
   <TD>selectmenu_highlight=7</TD>
</TR><TR ALIGN='LEFT'>   <TD>signaltreepanel_signal_tree_table=59</TD>
   <TD>simpleoutputproductdialog_generate_output_products_immediately=10</TD>
   <TD>simpleoutputproductdialog_reset_output_products=5</TD>
   <TD>smctreetablepanel_smc_tree_table=30</TD>
</TR><TR ALIGN='LEFT'>   <TD>srcmenu_ip_hierarchy=6</TD>
   <TD>srcmenu_refresh_hierarchy=2</TD>
   <TD>systembuildermenu_create_port=3</TD>
   <TD>systembuilderview_add_ip=3</TD>
</TR><TR ALIGN='LEFT'>   <TD>targetchooserpanel_target_chooser_table=9</TD>
   <TD>tclobjecttreetable_treetable=26</TD>
</TR>  </TABLE>
  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>java_command_handlers</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>addsources=1</TD>
   <TD>autoconnectport=17</TD>
   <TD>closedesign=1</TD>
   <TD>createblockdesign=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>createtophdl=9</TD>
   <TD>customizersbblock=11</TD>
   <TD>editdelete=11</TD>
   <TD>editproperties=4</TD>
</TR><TR ALIGN='LEFT'>   <TD>editundo=1</TD>
   <TD>launchopentarget=1</TD>
   <TD>managecompositetargets=16</TD>
   <TD>newexporthardware=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>newlaunchhardware=2</TD>
   <TD>openblockdesign=1</TD>
   <TD>openhardwaremanager=1</TD>
   <TD>regeneratersblayout=8</TD>
</TR><TR ALIGN='LEFT'>   <TD>runbitgen=4</TD>
   <TD>runsynthesis=1</TD>
   <TD>savedesign=1</TD>
   <TD>saversbdesign=3</TD>
</TR><TR ALIGN='LEFT'>   <TD>showview=5</TD>
   <TD>toolssettings=1</TD>
   <TD>validatersbdesign=5</TD>
   <TD>viewtasksynthesis=1</TD>
</TR>  </TABLE>
</TR><TR ALIGN='LEFT'>  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>other_data</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>guimode=2</TD>
</TR>  </TABLE>
  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>project_data</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>constraintsetcount=1</TD>
   <TD>core_container=false</TD>
   <TD>currentimplrun=impl_1</TD>
   <TD>currentsynthesisrun=synth_1</TD>
</TR><TR ALIGN='LEFT'>   <TD>default_library=xil_defaultlib</TD>
   <TD>designmode=RTL</TD>
   <TD>export_simulation_activehdl=10</TD>
   <TD>export_simulation_ies=10</TD>
</TR><TR ALIGN='LEFT'>   <TD>export_simulation_modelsim=10</TD>
   <TD>export_simulation_questa=10</TD>
   <TD>export_simulation_riviera=10</TD>
   <TD>export_simulation_vcs=10</TD>
</TR><TR ALIGN='LEFT'>   <TD>export_simulation_xsim=10</TD>
   <TD>implstrategy=Vivado Implementation Defaults</TD>
   <TD>launch_simulation_activehdl=0</TD>
   <TD>launch_simulation_ies=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>launch_simulation_modelsim=0</TD>
   <TD>launch_simulation_questa=0</TD>
   <TD>launch_simulation_riviera=0</TD>
   <TD>launch_simulation_vcs=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>launch_simulation_xsim=0</TD>
   <TD>simulator_language=Mixed</TD>
   <TD>srcsetcount=2</TD>
   <TD>synthesisstrategy=Vivado Synthesis Defaults</TD>
</TR><TR ALIGN='LEFT'>   <TD>target_language=Verilog</TD>
   <TD>target_simulator=XSim</TD>
   <TD>totalimplruns=2</TD>
   <TD>totalsynthesisruns=2</TD>
</TR>  </TABLE>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>unisim_transformation</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>post_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bibuf=130</TD>
    <TD>bufg=1</TD>
    <TD>fdre=22</TD>
    <TD>gnd=3</TD>
</TR><TR ALIGN='LEFT'>    <TD>ibuf=8</TD>
    <TD>lut1=112</TD>
    <TD>obuf=6</TD>
    <TD>obuft=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>ps7=1</TD>
    <TD>vcc=2</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>pre_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bibuf=130</TD>
    <TD>bufg=1</TD>
    <TD>fdre=22</TD>
    <TD>gnd=3</TD>
</TR><TR ALIGN='LEFT'>    <TD>ibuf=7</TD>
    <TD>iobuf=1</TD>
    <TD>lut1=112</TD>
    <TD>obuf=6</TD>
</TR><TR ALIGN='LEFT'>    <TD>ps7=1</TD>
    <TD>vcc=2</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>ip_statistics</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>IP_Integrator/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bdsource=USER</TD>
    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
    <TD>maxhierdepth=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>numblks=2</TD>
    <TD>numhdlrefblks=0</TD>
    <TD>numhierblks=0</TD>
    <TD>numhlsblks=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>numnonxlnxblks=0</TD>
    <TD>numpkgbdblks=0</TD>
    <TD>numreposblks=2</TD>
    <TD>numsysgenblks=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>synth_mode=OOC_per_IP</TD>
    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=BlockDiagram</TD>
    <TD>x_ipname=system</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=1.00.a</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>processing_system7_v5.5_user_configuration/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>iptotal=1</TD>
    <TD>pcw_apu_clk_ratio_enable=6:2:1</TD>
    <TD>pcw_apu_peripheral_freqmhz=666.666666</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_armpll_ctrl_fbdiv=40</TD>
    <TD>pcw_can0_grp_clk_enable=0</TD>
    <TD>pcw_can0_peripheral_clksrc=External</TD>
    <TD>pcw_can0_peripheral_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_can0_peripheral_freqmhz=-1</TD>
    <TD>pcw_can1_grp_clk_enable=0</TD>
    <TD>pcw_can1_peripheral_clksrc=External</TD>
    <TD>pcw_can1_peripheral_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_can1_peripheral_freqmhz=-1</TD>
    <TD>pcw_can_peripheral_clksrc=IO PLL</TD>
    <TD>pcw_can_peripheral_freqmhz=100</TD>
    <TD>pcw_cpu_cpu_pll_freqmhz=1333.333</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_cpu_peripheral_clksrc=ARM PLL</TD>
    <TD>pcw_crystal_peripheral_freqmhz=33.333333</TD>
    <TD>pcw_dci_peripheral_clksrc=DDR PLL</TD>
    <TD>pcw_dci_peripheral_freqmhz=10.159</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_ddr_ddr_pll_freqmhz=1066.667</TD>
    <TD>pcw_ddr_hpr_to_critical_priority_level=15</TD>
    <TD>pcw_ddr_hprlpr_queue_partition=HPR(0)/LPR(32)</TD>
    <TD>pcw_ddr_lpr_to_critical_priority_level=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_ddr_peripheral_clksrc=DDR PLL</TD>
    <TD>pcw_ddr_port0_hpr_enable=0</TD>
    <TD>pcw_ddr_port1_hpr_enable=0</TD>
    <TD>pcw_ddr_port2_hpr_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_ddr_port3_hpr_enable=0</TD>
    <TD>pcw_ddr_write_to_critical_priority_level=2</TD>
    <TD>pcw_ddrpll_ctrl_fbdiv=32</TD>
    <TD>pcw_enet0_enet0_io=EMIO</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_enet0_grp_mdio_enable=1</TD>
    <TD>pcw_enet0_peripheral_clksrc=External</TD>
    <TD>pcw_enet0_peripheral_enable=1</TD>
    <TD>pcw_enet0_peripheral_freqmhz=100 Mbps</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_enet0_reset_enable=0</TD>
    <TD>pcw_enet1_grp_mdio_enable=0</TD>
    <TD>pcw_enet1_peripheral_clksrc=IO PLL</TD>
    <TD>pcw_enet1_peripheral_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_enet1_peripheral_freqmhz=1000 Mbps</TD>
    <TD>pcw_enet1_reset_enable=0</TD>
    <TD>pcw_enet_reset_polarity=Active Low</TD>
    <TD>pcw_fclk0_peripheral_clksrc=IO PLL</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_fclk1_peripheral_clksrc=IO PLL</TD>
    <TD>pcw_fclk2_peripheral_clksrc=IO PLL</TD>
    <TD>pcw_fclk3_peripheral_clksrc=IO PLL</TD>
    <TD>pcw_fpga0_peripheral_freqmhz=100</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_fpga1_peripheral_freqmhz=50</TD>
    <TD>pcw_fpga2_peripheral_freqmhz=50</TD>
    <TD>pcw_fpga3_peripheral_freqmhz=50</TD>
    <TD>pcw_fpga_fclk0_enable=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_fpga_fclk1_enable=0</TD>
    <TD>pcw_fpga_fclk2_enable=0</TD>
    <TD>pcw_fpga_fclk3_enable=0</TD>
    <TD>pcw_ftm_cti_in0=DISABLED</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_ftm_cti_in1=DISABLED</TD>
    <TD>pcw_ftm_cti_in2=DISABLED</TD>
    <TD>pcw_ftm_cti_in3=DISABLED</TD>
    <TD>pcw_ftm_cti_out0=DISABLED</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_ftm_cti_out1=DISABLED</TD>
    <TD>pcw_ftm_cti_out2=DISABLED</TD>
    <TD>pcw_ftm_cti_out3=DISABLED</TD>
    <TD>pcw_gpio_emio_gpio_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_gpio_mio_gpio_enable=0</TD>
    <TD>pcw_gpio_peripheral_enable=0</TD>
    <TD>pcw_i2c0_grp_int_enable=0</TD>
    <TD>pcw_i2c0_peripheral_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_i2c0_reset_enable=0</TD>
    <TD>pcw_i2c1_grp_int_enable=0</TD>
    <TD>pcw_i2c1_peripheral_enable=0</TD>
    <TD>pcw_i2c1_reset_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_i2c_reset_polarity=Active Low</TD>
    <TD>pcw_io_io_pll_freqmhz=1600.000</TD>
    <TD>pcw_iopll_ctrl_fbdiv=48</TD>
    <TD>pcw_irq_f2p_mode=DIRECT</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_m_axi_gp0_freqmhz=10</TD>
    <TD>pcw_m_axi_gp1_freqmhz=10</TD>
    <TD>pcw_nand_cycles_t_ar=20</TD>
    <TD>pcw_nand_cycles_t_clr=20</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_nand_cycles_t_rc=40</TD>
    <TD>pcw_nand_cycles_t_rea=20</TD>
    <TD>pcw_nand_cycles_t_rr=40</TD>
    <TD>pcw_nand_cycles_t_wc=40</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_nand_cycles_t_wp=20</TD>
    <TD>pcw_nand_grp_d8_enable=0</TD>
    <TD>pcw_nand_nand_io=MIO 0 2.. 14</TD>
    <TD>pcw_nand_peripheral_enable=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_nor_cs0_t_ceoe=1</TD>
    <TD>pcw_nor_cs0_t_pc=1</TD>
    <TD>pcw_nor_cs0_t_rc=11</TD>
    <TD>pcw_nor_cs0_t_tr=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_nor_cs0_t_wc=11</TD>
    <TD>pcw_nor_cs0_t_wp=1</TD>
    <TD>pcw_nor_cs0_we_time=0</TD>
    <TD>pcw_nor_cs1_t_ceoe=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_nor_cs1_t_pc=1</TD>
    <TD>pcw_nor_cs1_t_rc=11</TD>
    <TD>pcw_nor_cs1_t_tr=1</TD>
    <TD>pcw_nor_cs1_t_wc=11</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_nor_cs1_t_wp=1</TD>
    <TD>pcw_nor_cs1_we_time=0</TD>
    <TD>pcw_nor_grp_a25_enable=0</TD>
    <TD>pcw_nor_grp_cs0_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_nor_grp_cs1_enable=0</TD>
    <TD>pcw_nor_grp_sram_cs0_enable=0</TD>
    <TD>pcw_nor_grp_sram_cs1_enable=0</TD>
    <TD>pcw_nor_grp_sram_int_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_nor_peripheral_enable=0</TD>
    <TD>pcw_nor_sram_cs0_t_ceoe=1</TD>
    <TD>pcw_nor_sram_cs0_t_pc=1</TD>
    <TD>pcw_nor_sram_cs0_t_rc=11</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_nor_sram_cs0_t_tr=1</TD>
    <TD>pcw_nor_sram_cs0_t_wc=11</TD>
    <TD>pcw_nor_sram_cs0_t_wp=1</TD>
    <TD>pcw_nor_sram_cs0_we_time=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_nor_sram_cs1_t_ceoe=1</TD>
    <TD>pcw_nor_sram_cs1_t_pc=1</TD>
    <TD>pcw_nor_sram_cs1_t_rc=11</TD>
    <TD>pcw_nor_sram_cs1_t_tr=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_nor_sram_cs1_t_wc=11</TD>
    <TD>pcw_nor_sram_cs1_t_wp=1</TD>
    <TD>pcw_nor_sram_cs1_we_time=0</TD>
    <TD>pcw_override_basic_clock=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_pcap_peripheral_clksrc=IO PLL</TD>
    <TD>pcw_pcap_peripheral_freqmhz=200</TD>
    <TD>pcw_pjtag_peripheral_enable=0</TD>
    <TD>pcw_preset_bank0_voltage=LVCMOS 3.3V</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_preset_bank1_voltage=LVCMOS 3.3V</TD>
    <TD>pcw_qspi_grp_fbclk_enable=0</TD>
    <TD>pcw_qspi_grp_io1_enable=0</TD>
    <TD>pcw_qspi_grp_single_ss_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_qspi_grp_ss1_enable=0</TD>
    <TD>pcw_qspi_internal_highaddress=0xFCFFFFFF</TD>
    <TD>pcw_qspi_peripheral_clksrc=IO PLL</TD>
    <TD>pcw_qspi_peripheral_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_qspi_peripheral_freqmhz=200</TD>
    <TD>pcw_s_axi_acp_freqmhz=10</TD>
    <TD>pcw_s_axi_gp0_freqmhz=10</TD>
    <TD>pcw_s_axi_gp1_freqmhz=10</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_s_axi_hp0_data_width=64</TD>
    <TD>pcw_s_axi_hp0_freqmhz=10</TD>
    <TD>pcw_s_axi_hp1_data_width=64</TD>
    <TD>pcw_s_axi_hp1_freqmhz=10</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_s_axi_hp2_data_width=64</TD>
    <TD>pcw_s_axi_hp2_freqmhz=10</TD>
    <TD>pcw_s_axi_hp3_data_width=64</TD>
    <TD>pcw_s_axi_hp3_freqmhz=10</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_sd0_grp_cd_enable=0</TD>
    <TD>pcw_sd0_grp_pow_enable=0</TD>
    <TD>pcw_sd0_grp_wp_enable=0</TD>
    <TD>pcw_sd0_peripheral_enable=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_sd0_sd0_io=MIO 40 .. 45</TD>
    <TD>pcw_sd1_grp_cd_enable=0</TD>
    <TD>pcw_sd1_grp_pow_enable=0</TD>
    <TD>pcw_sd1_grp_wp_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_sd1_peripheral_enable=0</TD>
    <TD>pcw_sdio_peripheral_clksrc=IO PLL</TD>
    <TD>pcw_sdio_peripheral_freqmhz=100</TD>
    <TD>pcw_smc_peripheral_clksrc=IO PLL</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_smc_peripheral_freqmhz=100</TD>
    <TD>pcw_spi0_grp_ss0_enable=0</TD>
    <TD>pcw_spi0_grp_ss1_enable=0</TD>
    <TD>pcw_spi0_grp_ss2_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_spi0_peripheral_enable=0</TD>
    <TD>pcw_spi1_grp_ss0_enable=0</TD>
    <TD>pcw_spi1_grp_ss1_enable=0</TD>
    <TD>pcw_spi1_grp_ss2_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_spi1_peripheral_enable=0</TD>
    <TD>pcw_spi_peripheral_clksrc=IO PLL</TD>
    <TD>pcw_spi_peripheral_freqmhz=166.666666</TD>
    <TD>pcw_tpiu_peripheral_clksrc=External</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_tpiu_peripheral_freqmhz=200</TD>
    <TD>pcw_trace_grp_16bit_enable=0</TD>
    <TD>pcw_trace_grp_2bit_enable=0</TD>
    <TD>pcw_trace_grp_32bit_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_trace_grp_4bit_enable=0</TD>
    <TD>pcw_trace_grp_8bit_enable=0</TD>
    <TD>pcw_trace_peripheral_enable=0</TD>
    <TD>pcw_ttc0_clk0_peripheral_clksrc=CPU_1X</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_ttc0_clk0_peripheral_freqmhz=133.333333</TD>
    <TD>pcw_ttc0_clk1_peripheral_clksrc=CPU_1X</TD>
    <TD>pcw_ttc0_clk1_peripheral_freqmhz=133.333333</TD>
    <TD>pcw_ttc0_clk2_peripheral_clksrc=CPU_1X</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_ttc0_clk2_peripheral_freqmhz=133.333333</TD>
    <TD>pcw_ttc0_peripheral_enable=0</TD>
    <TD>pcw_ttc1_clk0_peripheral_clksrc=CPU_1X</TD>
    <TD>pcw_ttc1_clk0_peripheral_freqmhz=133.333333</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_ttc1_clk1_peripheral_clksrc=CPU_1X</TD>
    <TD>pcw_ttc1_clk1_peripheral_freqmhz=133.333333</TD>
    <TD>pcw_ttc1_clk2_peripheral_clksrc=CPU_1X</TD>
    <TD>pcw_ttc1_clk2_peripheral_freqmhz=133.333333</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_ttc1_peripheral_enable=0</TD>
    <TD>pcw_ttc_peripheral_freqmhz=50</TD>
    <TD>pcw_uart0_baud_rate=115200</TD>
    <TD>pcw_uart0_grp_full_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uart0_peripheral_enable=0</TD>
    <TD>pcw_uart1_baud_rate=115200</TD>
    <TD>pcw_uart1_grp_full_enable=0</TD>
    <TD>pcw_uart1_peripheral_enable=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uart1_uart1_io=MIO 24 .. 25</TD>
    <TD>pcw_uart_peripheral_clksrc=IO PLL</TD>
    <TD>pcw_uart_peripheral_freqmhz=100</TD>
    <TD>pcw_uiparam_ddr_adv_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_al=0</TD>
    <TD>pcw_uiparam_ddr_bank_addr_count=3</TD>
    <TD>pcw_uiparam_ddr_bl=8</TD>
    <TD>pcw_uiparam_ddr_board_delay0=0.25</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_board_delay1=0.25</TD>
    <TD>pcw_uiparam_ddr_board_delay2=0.25</TD>
    <TD>pcw_uiparam_ddr_board_delay3=0.25</TD>
    <TD>pcw_uiparam_ddr_bus_width=16 Bit</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_cl=7</TD>
    <TD>pcw_uiparam_ddr_clock_0_length_mm=0</TD>
    <TD>pcw_uiparam_ddr_clock_0_package_length=54.563</TD>
    <TD>pcw_uiparam_ddr_clock_0_propogation_delay=160</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_clock_1_length_mm=0</TD>
    <TD>pcw_uiparam_ddr_clock_1_package_length=54.563</TD>
    <TD>pcw_uiparam_ddr_clock_1_propogation_delay=160</TD>
    <TD>pcw_uiparam_ddr_clock_2_length_mm=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_clock_2_package_length=54.563</TD>
    <TD>pcw_uiparam_ddr_clock_2_propogation_delay=160</TD>
    <TD>pcw_uiparam_ddr_clock_3_length_mm=0</TD>
    <TD>pcw_uiparam_ddr_clock_3_package_length=54.563</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_clock_3_propogation_delay=160</TD>
    <TD>pcw_uiparam_ddr_clock_stop_en=0</TD>
    <TD>pcw_uiparam_ddr_col_addr_count=10</TD>
    <TD>pcw_uiparam_ddr_cwl=6</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_device_capacity=2048 MBits</TD>
    <TD>pcw_uiparam_ddr_dq_0_length_mm=0</TD>
    <TD>pcw_uiparam_ddr_dq_0_package_length=104.5365</TD>
    <TD>pcw_uiparam_ddr_dq_0_propogation_delay=160</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_dq_1_length_mm=0</TD>
    <TD>pcw_uiparam_ddr_dq_1_package_length=70.676</TD>
    <TD>pcw_uiparam_ddr_dq_1_propogation_delay=160</TD>
    <TD>pcw_uiparam_ddr_dq_2_length_mm=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_dq_2_package_length=59.1615</TD>
    <TD>pcw_uiparam_ddr_dq_2_propogation_delay=160</TD>
    <TD>pcw_uiparam_ddr_dq_3_length_mm=0</TD>
    <TD>pcw_uiparam_ddr_dq_3_package_length=81.319</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_dq_3_propogation_delay=160</TD>
    <TD>pcw_uiparam_ddr_dqs_0_length_mm=0</TD>
    <TD>pcw_uiparam_ddr_dqs_0_package_length=101.239</TD>
    <TD>pcw_uiparam_ddr_dqs_0_propogation_delay=160</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_dqs_1_length_mm=0</TD>
    <TD>pcw_uiparam_ddr_dqs_1_package_length=79.5025</TD>
    <TD>pcw_uiparam_ddr_dqs_1_propogation_delay=160</TD>
    <TD>pcw_uiparam_ddr_dqs_2_length_mm=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_dqs_2_package_length=60.536</TD>
    <TD>pcw_uiparam_ddr_dqs_2_propogation_delay=160</TD>
    <TD>pcw_uiparam_ddr_dqs_3_length_mm=0</TD>
    <TD>pcw_uiparam_ddr_dqs_3_package_length=71.7715</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_dqs_3_propogation_delay=160</TD>
    <TD>pcw_uiparam_ddr_dqs_to_clk_delay_0=0.0</TD>
    <TD>pcw_uiparam_ddr_dqs_to_clk_delay_1=0.0</TD>
    <TD>pcw_uiparam_ddr_dqs_to_clk_delay_2=0.0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_dqs_to_clk_delay_3=0.0</TD>
    <TD>pcw_uiparam_ddr_dram_width=16 Bits</TD>
    <TD>pcw_uiparam_ddr_ecc=Disabled</TD>
    <TD>pcw_uiparam_ddr_enable=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_freq_mhz=533.333333</TD>
    <TD>pcw_uiparam_ddr_high_temp=Normal (0-85)</TD>
    <TD>pcw_uiparam_ddr_memory_type=DDR 3</TD>
    <TD>pcw_uiparam_ddr_partno=MT41K128M16 JT-125</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_row_addr_count=14</TD>
    <TD>pcw_uiparam_ddr_speed_bin=DDR3_1066F</TD>
    <TD>pcw_uiparam_ddr_t_faw=40.0</TD>
    <TD>pcw_uiparam_ddr_t_ras_min=35.0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_t_rc=48.75</TD>
    <TD>pcw_uiparam_ddr_t_rcd=7</TD>
    <TD>pcw_uiparam_ddr_t_rp=7</TD>
    <TD>pcw_uiparam_ddr_train_data_eye=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_uiparam_ddr_train_read_gate=1</TD>
    <TD>pcw_uiparam_ddr_train_write_level=1</TD>
    <TD>pcw_uiparam_ddr_use_internal_vref=0</TD>
    <TD>pcw_usb0_peripheral_enable=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_usb0_peripheral_freqmhz=60</TD>
    <TD>pcw_usb0_reset_enable=0</TD>
    <TD>pcw_usb1_peripheral_enable=0</TD>
    <TD>pcw_usb1_peripheral_freqmhz=60</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_usb1_reset_enable=0</TD>
    <TD>pcw_usb_reset_polarity=Active Low</TD>
    <TD>pcw_use_cross_trigger=0</TD>
    <TD>pcw_use_m_axi_gp0=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_use_m_axi_gp1=0</TD>
    <TD>pcw_use_s_axi_acp=0</TD>
    <TD>pcw_use_s_axi_gp0=0</TD>
    <TD>pcw_use_s_axi_gp1=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_use_s_axi_hp0=0</TD>
    <TD>pcw_use_s_axi_hp1=0</TD>
    <TD>pcw_use_s_axi_hp2=0</TD>
    <TD>pcw_use_s_axi_hp3=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcw_wdt_peripheral_clksrc=CPU_1X</TD>
    <TD>pcw_wdt_peripheral_enable=0</TD>
    <TD>pcw_wdt_peripheral_freqmhz=133.333333</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>processing_system7_v5_5_processing_system7/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_dm_width=4</TD>
    <TD>c_dq_width=32</TD>
    <TD>c_dqs_width=4</TD>
    <TD>c_emio_gpio_width=64</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_en_emio_enet0=1</TD>
    <TD>c_en_emio_enet1=0</TD>
    <TD>c_en_emio_pjtag=0</TD>
    <TD>c_en_emio_trace=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_fclk_clk0_buf=TRUE</TD>
    <TD>c_fclk_clk1_buf=FALSE</TD>
    <TD>c_fclk_clk2_buf=FALSE</TD>
    <TD>c_fclk_clk3_buf=FALSE</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_gp0_en_modifiable_txn=1</TD>
    <TD>c_gp1_en_modifiable_txn=1</TD>
    <TD>c_include_acp_trans_check=0</TD>
    <TD>c_include_trace_buffer=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_irq_f2p_mode=DIRECT</TD>
    <TD>c_m_axi_gp0_enable_static_remap=0</TD>
    <TD>c_m_axi_gp0_id_width=12</TD>
    <TD>c_m_axi_gp0_thread_id_width=12</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_m_axi_gp1_enable_static_remap=0</TD>
    <TD>c_m_axi_gp1_id_width=12</TD>
    <TD>c_m_axi_gp1_thread_id_width=12</TD>
    <TD>c_mio_primitive=54</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_num_f2p_intr_inputs=1</TD>
    <TD>c_package_name=clg400</TD>
    <TD>c_ps7_si_rev=PRODUCTION</TD>
    <TD>c_s_axi_acp_aruser_val=31</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_s_axi_acp_awuser_val=31</TD>
    <TD>c_s_axi_acp_id_width=3</TD>
    <TD>c_s_axi_gp0_id_width=6</TD>
    <TD>c_s_axi_gp1_id_width=6</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_s_axi_hp0_data_width=64</TD>
    <TD>c_s_axi_hp0_id_width=6</TD>
    <TD>c_s_axi_hp1_data_width=64</TD>
    <TD>c_s_axi_hp1_id_width=6</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_s_axi_hp2_data_width=64</TD>
    <TD>c_s_axi_hp2_id_width=6</TD>
    <TD>c_s_axi_hp3_data_width=64</TD>
    <TD>c_s_axi_hp3_id_width=6</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_trace_buffer_clock_delay=12</TD>
    <TD>c_trace_buffer_fifo_size=128</TD>
    <TD>c_trace_internal_width=2</TD>
    <TD>c_trace_pipeline_width=8</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_use_axi_nonsecure=0</TD>
    <TD>c_use_default_acp_user_val=0</TD>
    <TD>c_use_m_axi_gp0=0</TD>
    <TD>c_use_m_axi_gp1=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_use_s_axi_acp=0</TD>
    <TD>c_use_s_axi_gp0=0</TD>
    <TD>c_use_s_axi_gp1=0</TD>
    <TD>c_use_s_axi_hp0=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_use_s_axi_hp1=0</TD>
    <TD>c_use_s_axi_hp2=0</TD>
    <TD>c_use_s_axi_hp3=0</TD>
    <TD>core_container=NA</TD>
</TR><TR ALIGN='LEFT'>    <TD>iptotal=1</TD>
    <TD>use_trace_data_edge_detector=0</TD>
    <TD>x_ipcorerevision=6</TD>
    <TD>x_iplanguage=VERILOG</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=processing_system7</TD>
    <TD>x_ipproduct=Vivado 2017.4</TD>
    <TD>x_ipsimlanguage=MIXED</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=5.5</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>xlconcat_v2_1_1_xlconcat/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>dout_width=4</TD>
    <TD>in0_width=4</TD>
    <TD>in10_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in11_width=1</TD>
    <TD>in12_width=1</TD>
    <TD>in13_width=1</TD>
    <TD>in14_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in15_width=1</TD>
    <TD>in16_width=1</TD>
    <TD>in17_width=1</TD>
    <TD>in18_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in19_width=1</TD>
    <TD>in1_width=1</TD>
    <TD>in20_width=1</TD>
    <TD>in21_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in22_width=1</TD>
    <TD>in23_width=1</TD>
    <TD>in24_width=1</TD>
    <TD>in25_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in26_width=1</TD>
    <TD>in27_width=1</TD>
    <TD>in28_width=1</TD>
    <TD>in29_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in2_width=1</TD>
    <TD>in30_width=1</TD>
    <TD>in31_width=1</TD>
    <TD>in3_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in4_width=1</TD>
    <TD>in5_width=1</TD>
    <TD>in6_width=1</TD>
    <TD>in7_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>in8_width=1</TD>
    <TD>in9_width=1</TD>
    <TD>iptotal=1</TD>
    <TD>num_ports=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipcorerevision=1</TD>
    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=xlconcat</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipproduct=Vivado 2017.4</TD>
    <TD>x_ipsimlanguage=MIXED</TD>
    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=2.1</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_drc</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-append=default::[not_specified]</TD>
    <TD>-checks=default::[not_specified]</TD>
    <TD>-fail_on=default::[not_specified]</TD>
    <TD>-force=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-format=default::[not_specified]</TD>
    <TD>-messages=default::[not_specified]</TD>
    <TD>-name=default::[not_specified]</TD>
    <TD>-return_string=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-ruledecks=default::[not_specified]</TD>
    <TD>-upgrade_cw=default::[not_specified]</TD>
    <TD>-waived=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_methodology</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-append=default::[not_specified]</TD>
    <TD>-checks=default::[not_specified]</TD>
    <TD>-fail_on=default::[not_specified]</TD>
    <TD>-force=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-format=default::[not_specified]</TD>
    <TD>-messages=default::[not_specified]</TD>
    <TD>-name=default::[not_specified]</TD>
    <TD>-return_string=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-waived=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>results</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>ckld-2=2</TD>
    <TD>timing-17=12</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_power</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-advisory=default::[not_specified]</TD>
    <TD>-append=default::[not_specified]</TD>
    <TD>-file=[specified]</TD>
    <TD>-format=default::text</TD>
</TR><TR ALIGN='LEFT'>    <TD>-hier=default::power</TD>
    <TD>-l=default::[not_specified]</TD>
    <TD>-name=default::[not_specified]</TD>
    <TD>-no_propagation=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-return_string=default::[not_specified]</TD>
    <TD>-rpx=[specified]</TD>
    <TD>-verbose=default::[not_specified]</TD>
    <TD>-vid=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-xpe=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>airflow=250 (LFM)</TD>
    <TD>ambient_temp=25.0 (C)</TD>
    <TD>bi-dir_toggle=12.500000</TD>
    <TD>bidir_output_enable=1.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>board_layers=8to11 (8 to 11 Layers)</TD>
    <TD>board_selection=medium (10&quot;x10&quot;)</TD>
    <TD>clocks=0.000000</TD>
    <TD>confidence_level_clock_activity=Low</TD>
</TR><TR ALIGN='LEFT'>    <TD>confidence_level_design_state=High</TD>
    <TD>confidence_level_device_models=High</TD>
    <TD>confidence_level_internal_activity=Medium</TD>
    <TD>confidence_level_io_activity=Low</TD>
</TR><TR ALIGN='LEFT'>    <TD>confidence_level_overall=Low</TD>
    <TD>customer=TBD</TD>
    <TD>customer_class=TBD</TD>
    <TD>devstatic=0.115170</TD>
</TR><TR ALIGN='LEFT'>    <TD>die=xc7z010clg400-1</TD>
    <TD>dsp_output_toggle=12.500000</TD>
    <TD>dynamic=1.278965</TD>
    <TD>effective_thetaja=11.5</TD>
</TR><TR ALIGN='LEFT'>    <TD>enable_probability=0.990000</TD>
    <TD>family=zynq</TD>
    <TD>ff_toggle=12.500000</TD>
    <TD>flow_state=routed</TD>
</TR><TR ALIGN='LEFT'>    <TD>heatsink=none</TD>
    <TD>i/o=0.005133</TD>
    <TD>input_toggle=12.500000</TD>
    <TD>junction_temp=41.1 (C)</TD>
</TR><TR ALIGN='LEFT'>    <TD>logic=0.000004</TD>
    <TD>mgtavcc_dynamic_current=0.000000</TD>
    <TD>mgtavcc_static_current=0.000000</TD>
    <TD>mgtavcc_total_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>mgtavcc_voltage=1.000000</TD>
    <TD>mgtavtt_dynamic_current=0.000000</TD>
    <TD>mgtavtt_static_current=0.000000</TD>
    <TD>mgtavtt_total_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>mgtavtt_voltage=1.200000</TD>
    <TD>mgtvccaux_dynamic_current=0.000000</TD>
    <TD>mgtvccaux_static_current=0.000000</TD>
    <TD>mgtvccaux_total_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>mgtvccaux_voltage=1.800000</TD>
    <TD>netlist_net_matched=NA</TD>
    <TD>off-chip_power=0.000000</TD>
    <TD>on-chip_power=1.394135</TD>
</TR><TR ALIGN='LEFT'>    <TD>output_enable=1.000000</TD>
    <TD>output_load=5.000000</TD>
    <TD>output_toggle=12.500000</TD>
    <TD>package=clg400</TD>
</TR><TR ALIGN='LEFT'>    <TD>pct_clock_constrained=1.000000</TD>
    <TD>pct_inputs_defined=0</TD>
    <TD>platform=nt64</TD>
    <TD>process=typical</TD>
</TR><TR ALIGN='LEFT'>    <TD>ps7=1.273592</TD>
    <TD>ram_enable=50.000000</TD>
    <TD>ram_write=50.000000</TD>
    <TD>read_saif=False</TD>
</TR><TR ALIGN='LEFT'>    <TD>set/reset_probability=0.000000</TD>
    <TD>signal_rate=False</TD>
    <TD>signals=0.000236</TD>
    <TD>simulation_file=None</TD>
</TR><TR ALIGN='LEFT'>    <TD>speedgrade=-1</TD>
    <TD>static_prob=False</TD>
    <TD>temp_grade=commercial</TD>
    <TD>thetajb=9.3 (C/W)</TD>
</TR><TR ALIGN='LEFT'>    <TD>thetasa=0.0 (C/W)</TD>
    <TD>toggle_rate=False</TD>
    <TD>user_board_temp=25.0 (C)</TD>
    <TD>user_effective_thetaja=11.5</TD>
</TR><TR ALIGN='LEFT'>    <TD>user_junc_temp=41.1 (C)</TD>
    <TD>user_thetajb=9.3 (C/W)</TD>
    <TD>user_thetasa=0.0 (C/W)</TD>
    <TD>vccadc_dynamic_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccadc_static_current=0.020000</TD>
    <TD>vccadc_total_current=0.020000</TD>
    <TD>vccadc_voltage=1.800000</TD>
    <TD>vccaux_dynamic_current=0.000187</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccaux_io_dynamic_current=0.000000</TD>
    <TD>vccaux_io_static_current=0.000000</TD>
    <TD>vccaux_io_total_current=0.000000</TD>
    <TD>vccaux_io_voltage=1.800000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccaux_static_current=0.007561</TD>
    <TD>vccaux_total_current=0.007748</TD>
    <TD>vccaux_voltage=1.800000</TD>
    <TD>vccbram_dynamic_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccbram_static_current=0.000380</TD>
    <TD>vccbram_total_current=0.000380</TD>
    <TD>vccbram_voltage=1.000000</TD>
    <TD>vccint_dynamic_current=0.000272</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccint_static_current=0.006204</TD>
    <TD>vccint_total_current=0.006476</TD>
    <TD>vccint_voltage=1.000000</TD>
    <TD>vcco12_dynamic_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco12_static_current=0.000000</TD>
    <TD>vcco12_total_current=0.000000</TD>
    <TD>vcco12_voltage=1.200000</TD>
    <TD>vcco135_dynamic_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco135_static_current=0.000000</TD>
    <TD>vcco135_total_current=0.000000</TD>
    <TD>vcco135_voltage=1.350000</TD>
    <TD>vcco15_dynamic_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco15_static_current=0.000000</TD>
    <TD>vcco15_total_current=0.000000</TD>
    <TD>vcco15_voltage=1.500000</TD>
    <TD>vcco18_dynamic_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco18_static_current=0.000000</TD>
    <TD>vcco18_total_current=0.000000</TD>
    <TD>vcco18_voltage=1.800000</TD>
    <TD>vcco25_dynamic_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco25_static_current=0.000000</TD>
    <TD>vcco25_total_current=0.000000</TD>
    <TD>vcco25_voltage=2.500000</TD>
    <TD>vcco33_dynamic_current=0.001444</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco33_static_current=0.001000</TD>
    <TD>vcco33_total_current=0.002444</TD>
    <TD>vcco33_voltage=3.300000</TD>
    <TD>vcco_ddr_dynamic_current=0.354314</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco_ddr_static_current=0.002000</TD>
    <TD>vcco_ddr_total_current=0.356314</TD>
    <TD>vcco_ddr_voltage=1.500000</TD>
    <TD>vcco_mio0_dynamic_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco_mio0_static_current=0.000000</TD>
    <TD>vcco_mio0_total_current=0.000000</TD>
    <TD>vcco_mio0_voltage=1.800000</TD>
    <TD>vcco_mio1_dynamic_current=0.001375</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco_mio1_static_current=0.001000</TD>
    <TD>vcco_mio1_total_current=0.002375</TD>
    <TD>vcco_mio1_voltage=1.800000</TD>
    <TD>vccpaux_dynamic_current=0.025727</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccpaux_static_current=0.010330</TD>
    <TD>vccpaux_total_current=0.036057</TD>
    <TD>vccpaux_voltage=1.800000</TD>
    <TD>vccpint_dynamic_current=0.665583</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccpint_static_current=0.026881</TD>
    <TD>vccpint_total_current=0.692464</TD>
    <TD>vccpint_voltage=1.000000</TD>
    <TD>vccpll_dynamic_current=0.015420</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccpll_static_current=0.003000</TD>
    <TD>vccpll_total_current=0.018420</TD>
    <TD>vccpll_voltage=1.800000</TD>
    <TD>version=2017.4</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_utilization</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clocking</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufgctrl_available=32</TD>
    <TD>bufgctrl_fixed=0</TD>
    <TD>bufgctrl_used=0</TD>
    <TD>bufgctrl_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufhce_available=48</TD>
    <TD>bufhce_fixed=0</TD>
    <TD>bufhce_used=0</TD>
    <TD>bufhce_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufio_available=8</TD>
    <TD>bufio_fixed=0</TD>
    <TD>bufio_used=0</TD>
    <TD>bufio_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufmrce_available=4</TD>
    <TD>bufmrce_fixed=0</TD>
    <TD>bufmrce_used=0</TD>
    <TD>bufmrce_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufr_available=8</TD>
    <TD>bufr_fixed=0</TD>
    <TD>bufr_used=0</TD>
    <TD>bufr_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>mmcme2_adv_available=2</TD>
    <TD>mmcme2_adv_fixed=0</TD>
    <TD>mmcme2_adv_used=0</TD>
    <TD>mmcme2_adv_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>plle2_adv_available=2</TD>
    <TD>plle2_adv_fixed=0</TD>
    <TD>plle2_adv_used=0</TD>
    <TD>plle2_adv_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>dsp</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>dsps_available=80</TD>
    <TD>dsps_fixed=0</TD>
    <TD>dsps_used=0</TD>
    <TD>dsps_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>io_standard</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>blvds_25=0</TD>
    <TD>diff_hstl_i=0</TD>
    <TD>diff_hstl_i_18=0</TD>
    <TD>diff_hstl_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_hstl_ii_18=0</TD>
    <TD>diff_hsul_12=0</TD>
    <TD>diff_mobile_ddr=0</TD>
    <TD>diff_sstl135=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_sstl135_r=0</TD>
    <TD>diff_sstl15=1</TD>
    <TD>diff_sstl15_r=0</TD>
    <TD>diff_sstl18_i=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_sstl18_ii=0</TD>
    <TD>hstl_i=0</TD>
    <TD>hstl_i_18=0</TD>
    <TD>hstl_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>hstl_ii_18=0</TD>
    <TD>hsul_12=0</TD>
    <TD>lvcmos12=0</TD>
    <TD>lvcmos15=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lvcmos18=1</TD>
    <TD>lvcmos25=0</TD>
    <TD>lvcmos33=1</TD>
    <TD>lvds_25=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lvttl=0</TD>
    <TD>mini_lvds_25=0</TD>
    <TD>mobile_ddr=0</TD>
    <TD>pci33_3=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>ppds_25=0</TD>
    <TD>rsds_25=0</TD>
    <TD>sstl135=0</TD>
    <TD>sstl135_r=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>sstl15=1</TD>
    <TD>sstl15_r=0</TD>
    <TD>sstl18_i=0</TD>
    <TD>sstl18_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>tmds_33=0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>memory</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>block_ram_tile_available=60</TD>
    <TD>block_ram_tile_fixed=0</TD>
    <TD>block_ram_tile_used=0</TD>
    <TD>block_ram_tile_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb18_available=120</TD>
    <TD>ramb18_fixed=0</TD>
    <TD>ramb18_used=0</TD>
    <TD>ramb18_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb36_fifo_available=60</TD>
    <TD>ramb36_fifo_fixed=0</TD>
    <TD>ramb36_fifo_used=0</TD>
    <TD>ramb36_fifo_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>primitives</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bibuf_functional_category=IO</TD>
    <TD>bibuf_used=130</TD>
    <TD>fdre_functional_category=Flop &amp; Latch</TD>
    <TD>fdre_used=10</TD>
</TR><TR ALIGN='LEFT'>    <TD>ibuf_functional_category=IO</TD>
    <TD>ibuf_used=8</TD>
    <TD>lut1_functional_category=LUT</TD>
    <TD>lut1_used=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>obuf_functional_category=IO</TD>
    <TD>obuf_used=6</TD>
    <TD>obuft_functional_category=IO</TD>
    <TD>obuft_used=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>ps7_functional_category=Specialized Resource</TD>
    <TD>ps7_used=1</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>slice_logic</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>f7_muxes_available=8800</TD>
    <TD>f7_muxes_fixed=0</TD>
    <TD>f7_muxes_used=0</TD>
    <TD>f7_muxes_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>f8_muxes_available=4400</TD>
    <TD>f8_muxes_fixed=0</TD>
    <TD>f8_muxes_used=0</TD>
    <TD>f8_muxes_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_logic_available=17600</TD>
    <TD>lut_as_logic_fixed=0</TD>
    <TD>lut_as_logic_used=1</TD>
    <TD>lut_as_logic_util_percentage=&lt;0.01</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_memory_available=6000</TD>
    <TD>lut_as_memory_fixed=0</TD>
    <TD>lut_as_memory_used=0</TD>
    <TD>lut_as_memory_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_as_flip_flop_available=35200</TD>
    <TD>register_as_flip_flop_fixed=0</TD>
    <TD>register_as_flip_flop_used=10</TD>
    <TD>register_as_flip_flop_util_percentage=0.03</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_as_latch_available=35200</TD>
    <TD>register_as_latch_fixed=0</TD>
    <TD>register_as_latch_used=0</TD>
    <TD>register_as_latch_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_luts_available=17600</TD>
    <TD>slice_luts_fixed=0</TD>
    <TD>slice_luts_used=1</TD>
    <TD>slice_luts_util_percentage=&lt;0.01</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_registers_available=35200</TD>
    <TD>slice_registers_fixed=0</TD>
    <TD>slice_registers_used=10</TD>
    <TD>slice_registers_util_percentage=0.03</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_distributed_ram_fixed=0</TD>
    <TD>lut_as_distributed_ram_used=0</TD>
    <TD>lut_as_logic_available=17600</TD>
    <TD>lut_as_logic_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_logic_used=1</TD>
    <TD>lut_as_logic_util_percentage=&lt;0.01</TD>
    <TD>lut_as_memory_available=6000</TD>
    <TD>lut_as_memory_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_memory_used=0</TD>
    <TD>lut_as_memory_util_percentage=0.00</TD>
    <TD>lut_as_shift_register_fixed=0</TD>
    <TD>lut_as_shift_register_used=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_flip_flop_pairs_available=17600</TD>
    <TD>lut_flip_flop_pairs_fixed=0</TD>
    <TD>lut_flip_flop_pairs_used=0</TD>
    <TD>lut_flip_flop_pairs_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_available=4400</TD>
    <TD>slice_fixed=0</TD>
    <TD>slice_used=7</TD>
    <TD>slice_util_percentage=0.16</TD>
</TR><TR ALIGN='LEFT'>    <TD>slicel_fixed=0</TD>
    <TD>slicel_used=7</TD>
    <TD>slicem_fixed=0</TD>
    <TD>slicem_used=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>unique_control_sets_used=2</TD>
    <TD>using_o5_and_o6_fixed=2</TD>
    <TD>using_o5_and_o6_used=0</TD>
    <TD>using_o5_output_only_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>using_o5_output_only_used=0</TD>
    <TD>using_o6_output_only_fixed=0</TD>
    <TD>using_o6_output_only_used=1</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>specific_feature</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bscane2_available=4</TD>
    <TD>bscane2_fixed=0</TD>
    <TD>bscane2_used=0</TD>
    <TD>bscane2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>capturee2_available=1</TD>
    <TD>capturee2_fixed=0</TD>
    <TD>capturee2_used=0</TD>
    <TD>capturee2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>dna_port_available=1</TD>
    <TD>dna_port_fixed=0</TD>
    <TD>dna_port_used=0</TD>
    <TD>dna_port_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>efuse_usr_available=1</TD>
    <TD>efuse_usr_fixed=0</TD>
    <TD>efuse_usr_used=0</TD>
    <TD>efuse_usr_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>frame_ecce2_available=1</TD>
    <TD>frame_ecce2_fixed=0</TD>
    <TD>frame_ecce2_used=0</TD>
    <TD>frame_ecce2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>icape2_available=2</TD>
    <TD>icape2_fixed=0</TD>
    <TD>icape2_used=0</TD>
    <TD>icape2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>startupe2_available=1</TD>
    <TD>startupe2_fixed=0</TD>
    <TD>startupe2_used=0</TD>
    <TD>startupe2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>xadc_available=1</TD>
    <TD>xadc_fixed=0</TD>
    <TD>xadc_used=0</TD>
    <TD>xadc_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>router</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>actual_expansions=36914</TD>
    <TD>bogomips=0</TD>
    <TD>bram18=0</TD>
    <TD>bram36=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufg=0</TD>
    <TD>bufr=0</TD>
    <TD>congestion_level=0</TD>
    <TD>ctrls=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>dsp=0</TD>
    <TD>effort=2</TD>
    <TD>estimated_expansions=158610</TD>
    <TD>ff=10</TD>
</TR><TR ALIGN='LEFT'>    <TD>global_clocks=0</TD>
    <TD>high_fanout_nets=1</TD>
    <TD>iob=14</TD>
    <TD>lut=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>movable_instances=163</TD>
    <TD>nets=331</TD>
    <TD>pins=3654</TD>
    <TD>pll=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>router_runtime=0.000000</TD>
    <TD>router_timing_driven=1</TD>
    <TD>threads=2</TD>
    <TD>timing_constraints_exist=1</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>synthesis</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-assert=default::[not_specified]</TD>
    <TD>-bufg=default::12</TD>
    <TD>-cascade_dsp=default::auto</TD>
    <TD>-constrset=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-control_set_opt_threshold=default::auto</TD>
    <TD>-directive=default::default</TD>
    <TD>-fanout_limit=default::10000</TD>
    <TD>-flatten_hierarchy=default::rebuilt</TD>
</TR><TR ALIGN='LEFT'>    <TD>-fsm_extraction=default::auto</TD>
    <TD>-gated_clock_conversion=default::off</TD>
    <TD>-generic=default::[not_specified]</TD>
    <TD>-include_dirs=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-keep_equivalent_registers=default::[not_specified]</TD>
    <TD>-max_bram=default::-1</TD>
    <TD>-max_bram_cascade_height=default::-1</TD>
    <TD>-max_dsp=default::-1</TD>
</TR><TR ALIGN='LEFT'>    <TD>-max_uram=default::-1</TD>
    <TD>-max_uram_cascade_height=default::-1</TD>
    <TD>-mode=default::default</TD>
    <TD>-name=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-no_lc=default::[not_specified]</TD>
    <TD>-no_srlextract=default::[not_specified]</TD>
    <TD>-no_timing_driven=default::[not_specified]</TD>
    <TD>-part=xc7z010clg400-1</TD>
</TR><TR ALIGN='LEFT'>    <TD>-resource_sharing=default::auto</TD>
    <TD>-retiming=default::[not_specified]</TD>
    <TD>-rtl=default::[not_specified]</TD>
    <TD>-rtl_skip_constraints=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-rtl_skip_ip=default::[not_specified]</TD>
    <TD>-seu_protect=default::none</TD>
    <TD>-sfcu=default::[not_specified]</TD>
    <TD>-shreg_min_size=default::3</TD>
</TR><TR ALIGN='LEFT'>    <TD>-top=system_wrapper</TD>
    <TD>-verilog_define=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>elapsed=00:00:35s</TD>
    <TD>hls_ip=0</TD>
    <TD>memory_gain=489.605MB</TD>
    <TD>memory_peak=792.531MB</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
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